Hardware Implementation

Computing systems play a vital role in our society, influencing both industry and academia, and the spectrum of applications executing on these systems and their complexity varies widely. Future generations of computing systems are expected to execute processes which are more complex and larger in size. The tasks comprising these applications will have many constraints associated with their execution, and scheduling of such tasks using exact methods will become intractable or Non Polynomial (NP) complete. The NP completeness of the task scheduling problem has incited the use of various heuristics to obtain good solutions in a reasonable amount of time. In this thesis one such meta-heuristic known as a genetic algorithm (GA) is used. GAs are generic, domain independent search and optimization techniques based on the theory of evolution. GAs have been successfully applied to many classes of scheduling problems. However, with the increase in the size of the scheduling problem, the time complexity of the software implementation of a GA becomes high. To reduce the time complexity without compromising the solution quality, GAs have been parallelized. However, parallelization demands additional resources leading to a poor cost performance tradeoff. The advent of hardware technologies and design tools in the field of reconfigurable devices has enabled us to achieve better cost performance tradeoff. This thesis explores one such approach where a parallelized hardware-based GA task scheduler is implemented and its performance is compared to that of parallelized software-based GA.